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NT6880
Keyboard Controller
Features
T T T T T T T
Built-in 6502 8-bit CPU 2 MHz CPU operation frequency 5K bytes of ROM 160 bytes of SRAM One 8-bit programmable base timer with 1 - 256 sec interval 29 programmable bi-directional I/O pins 3 LED direct sink pins
T T T T T T T
Mask optional for built-in RC oscillator with an external resistor or external ceramic resonator applied Mask optional for DATA/CLK driving capability Watch-dog timer reset Built-in power-on reset Built-in low voltage reset CMOS technology for low power consumption Available in 40 pin DIP package and 40 pad Chip Form
General Description
The NT6880 is a single chip micro-controller for keyboard applications. It incorporates a 6502 8-bit CPU core, 5K bytes of ROM and 160 bytes of RAM used as working RAM and stack area. It also includes 29 programmable bi-directional I/O pins and one 8-bit preloadable base timer. Additionally, it includes a built-in low voltage reset, a 4MHz RC oscillator requiring an externally applied resistor or a 4MHz ceramic resonator and a watch-dog timer that prevents system standstill.
Pin Configuration
Pad Configuration
P 1 7 P 1 6 P 1 5 P 1 4 P 1 3 P 1 2 P 1 1 P 1 0 P 0 7 P 0 6
GND NC DATA CLK P30 P31 P32 P33 P34 RESET P00 P01 P02 P03 P04 P05 P06 P07 P10 P11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
OSCI R/OSCO V DD LED2 LED1 LED0 P27 P26 P25 P24 P23 P22 P21 P20 P17 P16 P15 P14 P13 P12
LED1 36 P20 P21 P22 P23 P24 P25 P26 P27 LED0 27 28 29 30 31 32 33 34 35 37 38 39 40 1 2 3 4 5 6 P31 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 P05 P04 P03 P02 P01 P00 RESET P34 P33 P32
NT6880
NT6880H
L E D 2
V
D D
R / O S C O
O S C I
G N D
N C
D A T A
C L K
P 3 0
1
V1.0
NT6880
Block Diagram
CLK Timing Generator (RC OSC/Ceramic Resonator: 4MHz) 5K Bytes ROM
DATA
LED0
LED1
6502 CPU
160 Bytes SRAM + STACK
LED2
I/O PORTs
P00 - P07
Interrupt Controller
Watch Dog Timer
P10 - P17
P20 - P27 RESET V DD GND Power-On RESET/ Low Voltage RESET Base Timer P30 - P34
Pin and Pad Descriptions
Pin No. 1 2 3 4 5 - 9, 11 - 34 10 35 - 37 38 39 40 Pad No. 1 2 3 4 5 - 9, 11 - 34 10 35 - 37 38 39 40 Designation GND NC DATA CLK P30 - P34, P00 - P27
RESET
I/O P I/O I/O I/O I O P I Ground pin
Description No connection, recommended to connect VDD or floating I/O, 10K pull-up resistor for communication I/O, 10K pull-up resistor for communication Bi-directional I/O pins
RESET signal input pin with internal pull up resistor; Active low
LED0 LED2 VDD R/OSCO OSCI
LED direct sink pins Power supply 47K resistor connected for RC OSC or 4MHz ceramic resonator connected No connection for RC OSC connected for 4MHz ceramic resonator
* Under the constraint of the maximum frequency variation, (F/F)max, 1%, code 3, 7 (ceramic resonator option) must be selected and pin 39 and pin 40 must be connected to a ceramic resonator. If (F/F)max, 10%, code 1, 5 (RC OSC option) it is recommended that pin 39 be connected to a 47K resistor with 1% accuracy to VDD. Pin 40 is floating.
2
NT6880
Functional Description
1. 6502 CPU The 6502 is an 8-bit CPU. Please refer to the 6502 data sheet for more details.
7 ACCUMULATOR A 7 INDEX REGISTER X
0 0000 SRAM 0 009F UNUSED 00C0 0 INDEX REGISTER Y SYSTEM REGISTERS 00CF STACK PTR
7
15 PROGRAM COUNTER PC 7 S 7 S V B D I Z
0
UNUSED
0 STACK POINTER SP 0 C STATUS REGISTER P
EC00
USER ROM
FFFA CARRY FFFB ZERO INTERRUPT MASK DECIMAL MODE BREAK OVERFOLW SIGN FFFC RST-L FFFD RST-H FFFE IRQ-L FFFF IRQ-H IRQ VECTOR NMI-H NMI-L NMI VECTOR
Figure 1.1 6502 CPU Registers and Status Flags
Figure 1.2. NT6880 Memory Map
3
NT6880
2. System Reserved Registers Addr. $00C0 $00C1 $00C2 $00C3 $00C4 $00C5 $00C6 $00C7 $00C8 $00C9 $00CA $00CB $00CC $00CD $00CE $00CF - : no effect 3. ROM: 5K X 8 bits The built-in ROM program code, executed by the 6502 CPU, has a capacity of 5K X 8 bits and is addressed from EC00H to FFFFH. 4. SRAM: 160 X 8 bits The built-in SRAM is used for general purpose data memory and for the stack area. SRAM is addressed from 0000H to 009FH. User can allocate stack area in the SRAM by setting stack pointer register (S). Because the 6502 default stack pointer is 01FFH, it must be mapped to 009FH. Mapping from 01XX to 00XX is done internally by setting the S register to 9FH via software programming. For example : LDX #$9F TXS For compatibility to UM6868A with 128-byte SRAM, the user's source code can not be changed. For example : LDX TXS #$7F
power V DD 60% The start of 150ms pulse t
Register BT TCON CLRIRQX PORT0 PORT1 PORT2 PORT3 CLK DATA LED CLRWDT X X X X X
Bit7 BT7 PD07 PD17 PD27 0 X X X X X
Bit6 BT6 PD06 PD16 PD26 1 X X X X X
Bit5 BT5 PD05 PD15 PD25 0 X X X X X
Bit4 BT4 PD04 PD14 PD24 PD34 1 X X X X X
Bit3 BT3 PD03 PD13 PD23 PD33 0 X X X X X
Bit2 BT2 PD02 PD12 PD22 PD32 LED2 1 X X X X X
Bit1 BT1 PD01 PD11 PD21 PD31 LED1 0 X X X X X
Bit0 BT0
ENBT
R/W W W W RW RW RW RW RW RW W W X X X X X
CLRIRQTMR PD00 PD10 PD20 PD30 CLK DATA LED0 1 X X X X X
X : access not allowed 5. Power-On Reset Built-in power-on reset circuit can generate a 150ms pulse to reset the entire chip. The beginning of the 150ms pulse occurs at 60% of VDD when powered on.
Figure 5.1. Power-On Reset Timing
4
NT6880
The following table provides the relationship between external resistor and RC OSC frequency. (for reference only) External Resistor (K) 39 43 47 56 RC OSC Frequency (MHz) 4.7 4.44 4 3.68
6. Timing Generator This block generates the system timing and control signal supplied to the CPU and on-chip peripherals. There are two types of system clock sources: built-in RC oscillator or external ceramic resonator. Both are mask optional and generate a 4MHz system clock. They also generate 2MHz for the CPU, and 1 MHz for base timer.
7. Base Timer (BT) The base timer is an 8-bit counter with a 1MHz clock source. The base timer can be enabled/disabled by CPU. After reset, the base timer is disabled and cleared. The base timer can be preset by writing BT7 - BT0 to the BT register at any time. When enabled, the base timer starts counting from the preset value. When the value reaches FFH, it generates a timer interrupt if the timer interrupt is enabled. When it reaches the maximum value of FFH, the base timer will wrap around and begin counting at 00H. The timer interval can be programmed from 1 - 256 sec. The base timer can be enabled by writing a '0' to ' ENBT ' in the TCON (Timer Control) register. The ENBT is a level trigger. Base timer structure: 8-Bit timer 1s BT pre-load data: Addr. $00C0 Timer Control Register: $00C1 TCON ENBT
BT7
BT6
BT5
BT4
BT2
BT2
BT1
BT0
TMRINT
Bit BT
7 BT7
6 BT6
5 BT5
4 BT4
3 BT3
2 BT2
1 BT1
0 BT0
R/W (W)
(W)
8. Interrupt Controller When a BASE TIMER overflow occurs, it will set the IRQTMR flag. The IRQTMR flag cannot be directly accessed by the software. Once set by an interrupt source, it remains High unless cleared by writing '1' to the corresponding bit in CLRIRQX ($00C2H). This register is cleared to '0' on initialization by a system reset. When an interrupt occurs, the CPU will jump to $FFFEH & $FFFFH to execute an interrupt service routine. When the BASE TIMER interrupt occurs and enters an interrupt service routine, the IRQTMR flag must be cleared by the software. Interrupt Control Register: Addr. $00C2 Bit CLRIRQX 7 6 5 4 3 2 1 0 CLRIRQTMR R/W (W)
5
NT6880
9. I/O PORTs The NT6880 has 31 pins dedicated to input and output. These pins are grouped into 6 ports, as follows: 9.1. PORT0: (P00 - P07) PORT0 is an 8-bit bi-directional CMOS I/O port that is internally pulled High by PMOS. Each pin of PORT0 can be bit programmed as an input or output pin under the software control. When programmed as output, data is latched to the port data register and output to the pin. PORT0 pins with ''1'' written to them are pulled high by the internal PMOS pull-ups, and are used as inputs in that state. These input signals can then be read. The port output is High after reset. 9.2. PORT1: ( P10 - P17 ): Functions are the same as PORT0. 9.3. PORT2: ( P20 - P27) : Functions are the same as PORT0. 9.4. PORT3: ( P30 - P34) : Functions are the same as PORT0. CLK & DATA PORT Registers: Addr. $00C3 $00C4 $00C5 $00C6 $00C7 $00C8 Register PORT0 PORT1 PORT2 PORT3 CLK DATA Bit7 PD07 PD17 PD27 Bit6 PD06 PD16 PD26 Bit5 PD05 PD15 PD25 Bit4 PD04 PD14 PD24 PD34 Bit3 PD03 PD13 PD23 PD33 Bit2 PD02 PD12 PD22 PD32 Bit1 PD01 PD11 PD21 PD31 Bit0 PD00 PD10 PD20 PD30 CLK DATA R/W (RW) (RW) (RW) (RW) (RW) (RW) : These two pins have the same structure as I/O ports.
V DD Latch WREN L Q DB D RST SD IO Weak PMOS
RDENB
Figure 9.1. I/O Port Structure
6
NT6880
10. LED PORT There are 3 LED direct sink pins which require no external serial resistors. The address is mapped to address $00C9. Addr. $00C9 Register LED Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 LED2 Bit1 LED1 Bit0 LED0 R/W (W)
WREN L Q DB D RST SD
LED [ 0 ]
V DD WREN L Q DB D RST SD LED [ 1:2 ]
Figure 10.1. LED0 Port Structure 11. Watch-Dog Timer (WDT)
Figure 10.2. LED1, LED2 Port Structures
NT6880 implements a watch-dog timer, which protects programs against system standstill. The clock of the watch-dog timer is derived from the on-chip RC oscillator. The watch-dog timer interval is about 0.175 of a second. The timer must be cleared within every 0.175 second during normal operation; otherwise, it will overflow and cause a system reset. The watch-dog timer is cleared and enabled after a system reset. It cannot be disabled by the software. A user can clear the watch-dog timer by writing #55H to CLRWDT ($00CAH) register. For example: LDA STA Addr. $00CA Register CLRWDT
#$55 $00CA Bit7 0 Bit6 1 Bit5 0 Bit4 1 Bit3 0 Bit2 1 Bit1 0 Bit0 1 R/W (W)
12. Low Voltage Reset (LVR) Circuit The NT6880 will check on the voltage level of power supply. When the voltage level of power supply is below a threshold of 3.0V (Typical), the LVRC will issue a reset output to the chip until the power voltage level is above the threshold voltage of 3.0V (Typical) again. As soon as the power voltage arises to 3.0V (Typical), the entire chip will be reset for about 150ms. 13. RESET NT6880 can also be externally reset via the RESET pin. A reset is initiated when the signal at the RESET pin is held Low for at least 10 system clocks. As soon as the RESET signal goes high, the NT6880 begins to be reset for about 150ms. The following shows the definition of the RESET input low pulse width.
V DD V DD
20%V
DD
20%V Trstb
DD
7
NT6880
Absolute Maximum Ratings*
DC Supply Voltage . . . . . . . . . . . . . . . -0.3V to +7.0V Input/Output Voltage . . . . . . GND -0.2V to VDD + 0.2V Operating Ambient Temperature . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . -55C to +125C Operating Voltage (VDD) . . . . . . . . . . . . . +4.5V to 5.5V
*Comments
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
DC Electrical Characteristics (VDD = 5V, GND = 0V, TA = 25C, FOSC = 4MHz, unless otherwise specified)
Symbol ICC VIH VIL VOH1 VOH2 VOH3 VOL1 VOL2 VOL3 F/F F/F ILED VLVR TPOR TRSTB RPH Parameter Power Supply Current Input High Voltage Input Low Voltage Output High Voltage (PORT 0, 1, 2, 3) Output High Voltage (CLK, DATA) Output High Voltage (CLK, DATA) Output Low Voltage (PORT 0, 1, 2) Output Low Voltage (PORT 3) Output Low Voltage (CLK, DATA) Initial Frequency Variation 1 Frequency Variation 2 LED Sink Current (LED 0, 1, 2) Low Voltage Reset Threshold Power-on Reset Time
RESET Input Low Pulse Width RESET Pull High Resistor
Min.
Typ.
Max. 20
Unit mA V
Conditions No load
2 0.8 2.4 2.4 2.4 0.4 0.4 0.4 +/-10 +/-1 10 14 3.0 120 2.5 220 150 180 17
V V V V V V V % % mA V ms s K 10 system clocks IOH1 = -100A IOH2 = -400A, Note 1 IOH3 = -800A, Note 2 IOL1 = 4mA IOL2 = 5mA IOL3 = 10mA For RC OSC option only; by Lots For ceramic resonator option only; by Lots VOL = 3.2V
Note 1: There are 2 types for DATA/CLK driving capability. The specification of VOH2 is the same as NT6868A. Under this condition, user can select mask option 1 or 3 for this specification. Note 2: The driving capability of DATA/CLK is higher than V OH2. Under this condition, a user can select mask option 5 or 7 for this specification.
8
NT6880
Application Circuit I (for reference only)
V DD 4.7 - 10 m f
P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P30 P31
VDD
VDD GND Scroll Lock LED0 Num Lock LED1 Caps Lock LED2 0.1m f RESET Optional
NT6880
DATA CLK KBD DATA KBD CLOCK VDD R/OSCO 47K (System clock can be decreased by increasing the resistance)
P20 P21 P22 P23 P24 P25 P26 P27
R0
R1
R2
R3
R4 (R) Ctrl
R5
R6 (L) Ctrl
R7
S0 S1 S2 S3 S4 S5 S6 S7
Pause Q W E R U I O Tab Caps Lock F3 T Y } ] F7 { [ A S D F J K L : ; " ' (L) Alt Back Space 4 5 6 | \(K29) 1 End 2 3 PgDn (R) F11 Space 0 Ins . Del Esc (K45) Macro F4 G H F6
F5 ! 1 @ 2 # 3 $ 4 & 7 * 8 ( 9 ) 0 Print Screen
Z X C V M < , > . | \(K42)
K131 K132 K133 B N K56 APP ? / (R) Alt
~ , F1 F2 % 5 ^ 6 + = F8
S8 S9 S10 S11 S12 9 S13 S14 S15 S16 S17
P Scroll Lock K14 7 Home 8
-
Enter Num Lock / *
F12
F9 Delete Insert
F10
PgUp +
-
Page Up
Page Down
K107 (L) Shift WINL
Enter (R) Shift
Home
End
WINR
9
NT6880
Application Circuit II (for reference only)
V DD 4.7 - 10 mf
V DD P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P30 P31 NT6880 LED2 0.1 mf RESET Optional LED1 Caps Lock V DD GND Scroll Lock LED0 Num Lock
DATA
KBD DATA
CLK P20 P21 P22 P23 P24 P25 P26 P27
KBD CLOCK
R/OSCO 4MHz Ceramic Resonator OSCI
R0
R1
R2
R3
R4 (R)
R5
R6 (L) Ctrl ~
R7
S0
Pause
Ctrl
F5 ! 1 @
S1
Q
Tab Caps
A
Esc (K45)
Z
K131
,
S2
W
Lock
S
Macro
X
K132
F1
2 #
S3
E
F3
D
F4
C
K133
F2 %
3 $ 4 & 7 * 8 (
S4
R
T
F
G
V
B
5 ^
S5
U
Y } ]
J
H
M < , >
N
6 + =
S6
I
K
F6
K56
S7
O
F7 {
L : ; " ' (L) Alt |
.
APP ?
F8
9 )
S8
P Scroll
[
\(K42)
/ (R) Alt
-
0 Print Screen
S9
Lock Back | \(K29) 1 End 5 2 0
S10 7 S11
K14
Space 4
F11
Enter Num
F12
F9
F10
Home 8
Space
Lock
Delete
S12 9 S13 PgUp 6 3 PgDn (R) S14 + K107 (L) S15 Shift Enter (R) Shift
Ins . Del
/
Insert Page * Up Page Down
Home
End
S16
WINL
S17
WINR
10
NT6880
Bonding Diagram
P 1 7 P 1 6 P 1 5 P 1 4 P 1 3 P 1 2 P 1 1 P 1 0 P 0 7 P 0 6
26
25
24
23
22
21
20
19
18
17
16 15
P05 P04 P03 P02 P01 P00 1760 m RESET P34 P33 P32
P20 P21 P22 P23 P24 P25 P26 P27 LED0 LED1
27 28 29 30 31 32 33 34 35 36 37 38 39
NT6880H
Y
14 13 12 11 X 10 9 8 7
(0, 0)
40
1
2
3
4
5
6
P31
L E D 2
V
D D
R / O S C O
O S C I
G N D
N C
D A T A
C L K
P 3 0
2000 m
*Substrate Connect to VDD unit: m Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Designation GND NC DATA CLK P30 P31 P32 P33 P34 RESET P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 X -126.4 3.6 133.6 393.6 619.4 865.0 870.2 870.2 870.2 870.2 870.2 870.2 870.2 870.2 870.2 870.2 374.1 244.1 114.1 -15.9 Y -687.1 -752.0 -752.0 -752.0 -752.0 -733.1 -435.6 -305.6 -175.6 -45.6 84.4 214.4 344.4 474.4 604.4 746.9 752.5 752.5 752.5 752.5 Pad No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Designation P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 LED0 LED1 LED2 VDD R/OSCO OSCI X -145.9 -275.9 -405.9 -535.9 -665.9 -808.4 -870.2 -870.2 -870.2 -870.2 -870.2 -870.2 -870.2 -870.2 -870.2 -870.2 -646.4 -516.4 -386.4 -256.4 Y 752.5 752.5 752.5 752.5 752.5 752.5 544.3 414.3 284.3 154.3 24.3 -105.7 -235.7 -365.7 -495.7 -641.8 -636.6 -636.6 -636.6 -636.6
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NT6880
Ordering Information
Part No. NT6880H NT6880 Packages CHIP FORM 40L DIP
Code Type No. 1XXXX 3XXXX 5XXXX 7XXXX
Oscillation Type Built-in RC OSC Ceramic Resonator Built-in RC OSC Ceramic Resonator
Data/Clk Driving capacitance V OH2 V OH2 V OH3 V OH3
12
NT6880
Package Information DIP 40L Outline Dimensions
D 40 21
unit: inches/mm
E1
1 S
20 E C
A2
A
A1
Base Plane
Seating Plane B B1 e1 eA
L
Symbol A A1 A2 B
Dimensions in inches 0.210 Max. 0.010 Min. 0.1550.010 0.018 +0.004 -0.002 0.050 +0.004 -0.002 0.010 +0.004 -0.002 2.055 Typ. (2.075 Max.) 0.6000.010 0.550 Typ. (0.562 Max.) 0.1000.010 0.1300.010 0 ~ 15 0.6550.035 0.093 Max.
Dimensions in mm 5.33 Max. 0.25 Min. 3.940.25 0.46 +0.10 -0.05 1.27 +0.10 -0.05 0.25 +0.10 -0.05 52.20 Typ. (52.71 Max.) 15.240.25 13.97 Typ. (14.27 Max.) 2.540.25 3.300.25 0 ~ 15 16.640.89 2.36 Max.
B1
C D E E1 e1 L eA S
Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E1 does not include resin fins. 3. Dimension S includes end flash.
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